The present invention relates to a semiconductor package having an anode and a cathode. As an example, FIGS. 1 and 2 illustrate a conventional diode package 1 in the form of a semiconductor package having two electrodes, i.e., an anode and a cathode. FIG. 1 is a diagrammatic perspective view, and FIG. 2 is a partial sectional view thereof.
In FIG. 1, two lead frames 2 and 3 are arranged on nearly the same axis; a semiconductor chip 4 is bonded onto the surface of the one lead frame 2 by a eutectic junction or press adhesion; a gold wire 5 is connected at one end to the surface of the semiconductor chip 4; and the surface of the semiconductor chip 4 is electrically connected to the other lead frame 3 through the gold wire 5. The semiconductor chip 4, gold wire 5 and lead frames 2, 3 are molded with a resin 6, which has a nearly rectangular parallelopiped outer shape.
An electric current flows between the lead frames 2 and 3 in the direction of the thickness of the semiconductor chip 4. The diode package 1 has a size measuring, as the outer shape of the resin 6, about 1.0 mm long, about 0.6 mm wide and about 0.55 mm high. The semiconductor chip 4 embedded in the resin 6 measures 0.3 mm long, about 0.3 mm wide and about 0.15 mm high.
JP-A-8-306853 discloses a semiconductor package having a package size that is larger than the diode package and having three or more electrodes, i.e., having a structure in which many electrode pads and many leads are formed on the surface of a semiconductor chip. In this package, the electrode pads and the leads are connected together through wires; bump electrodes are formed on the portions of the leads; and the surfaces of the leads and the side surfaces of the semiconductor chip are sealed with a resin in such a way that the ends and side surfaces of the bump electrodes and the back surface of the semiconductor chip are exposed.